Semiconductor devices having improved electrical characteristics and methods of fabricating the same

ABSTRACT

The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. nonprovisional application is a continuation of U.S. patent application Ser. No. 16/879,009 filed on May 20, 2020, which claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2019-0113475, filed on Sep. 16, 2019, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices and methods of fabricating the same, and more particularly, to semiconductor devices with improved electrical characteristics and methods of fabricating the same.

BACKGROUND

Semiconductor devices are considered to be important to electronic industry because of their small size, multi-functionality, and/or low fabrication cost. As the electronic industry has developed, semiconductor devices have become increasingly integrated. For example, line widths of patterns of semiconductor devices are being reduced for high integration of the semiconductor devices. However, new exposure techniques and/or expensive exposure techniques are required to achieve increased fineness of the patterns. As such, it is difficult to highly integrate semiconductor devices. Various studies have thus recently been conducted for new integration techniques.

SUMMARY

Some example embodiments of the present inventive concepts provide semiconductor devices with improved electrical characteristics.

An object of the present inventive concepts is not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description.

According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a substrate that includes a plurality of active regions that extend in a first direction and a device isolation layer that define the active regions; a plurality of word lines that extend across the active regions in a second direction that intersects the first direction; a plurality of bit-line structures that intersect the active regions and the word lines and that extend in a third direction perpendicular to the second direction; a plurality of first contacts between the bit-line structures and the active regions; a plurality of spacer structures on sidewalls of the bit-line structures; and a plurality of second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures may extend from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a substrate that includes a plurality of active regions that extend in a first direction and a device isolation layer that defines the active regions; a plurality of word lines that extend across the active regions in a second direction that intersect the first direction; a plurality of bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction; a plurality of dielectric patterns on the bit-line structures; a plurality of first contacts between the bit-line structures and the active regions; a plurality of spacer structures on sidewalls of the bit-line structures and sidewalls of the dielectric patterns; a plurality of separation patterns on the word lines and between adjacent bit-line structures; a plurality of second contacts between the separation patterns and between adjacent bit-line structures; a plurality of landing pads on top surfaces of the second contacts, top surfaces of the spacer structures, and top surfaces of the dielectric patterns; and a plurality of bottom electrodes on the landing pads. The spacer structures may include: a plurality of first parts in contact with the first contacts and a plurality of second parts between the first parts. The second parts may be in contact with the device isolation layer.

According to some example embodiments of the present inventive concepts, a method of fabricating a semiconductor device may comprise: forming on a substrate a device isolation layer that defines a plurality of active regions; forming a plurality of word lines on the substrate; forming a first contact hole by etching a portion of the substrate; and forming a contact pattern and a conductive layer on the contact pattern. The contact pattern may fill the first contact hole. The method may further include forming a plurality of bit-line structures by etching the contact pattern and the conductive layer; forming a second contact hole by etching the active region between the bit-line structures; forming a first buried contact in a lower portion of the second contact hole; forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and forming a second buried contact between the spacer structures. The second buried contact may fill the second contact hole. The spacer structure may be formed after the first buried contact is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a plan view showing a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 1B illustrates a cross-sectional view taken along line I-I′ of FIG. 1A, showing a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 1C illustrates an enlarged view showing section A of FIG. 1B.

FIGS. 2A to 18A illustrate plan views showing operations of methods for fabricating semiconductor devices according to some example embodiments of the present inventive concepts.

FIGS. 2B to 18B illustrate cross-sectional views taken along line I-I′ of FIGS. 2A to 18A, respectively, showing operations of methods for fabricating a semiconductor device according to some example embodiments of the present inventive concepts.

FIG. 19 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts.

FIGS. 20 and 21 illustrate cross-sectional views showing operations of methods of fabricating semiconductor devices according to some example embodiments of the present inventive concepts.

FIG. 22 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts.

FIGS. 23 and 24 illustrate cross-sectional views showing operations of methods of fabricating semiconductor devices according to some example embodiments of the present inventive concepts.

DETAILED DESCRIPTION

Semiconductor devices according to some example embodiments of the present inventive concepts will be described below in detail with reference to the accompanying drawings.

FIG. 1A illustrates a plan view showing a semiconductor device according to some example embodiments of the present inventive concepts. FIG. 1B illustrates a cross-sectional view taken along line I-I′ of FIG. 1A, showing a semiconductor device according to some example embodiments of the present inventive concepts. FIG. 1C illustrates an enlarged view showing section A of FIG. 1B.

Referring to FIGS. 1A to 1C, a substrate 100 may be provided that includes a device isolation layer 110 therein. The substrate 100 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or an epitaxial layer substrate obtained by performing selective epitaxial growth (SEG).

The device isolation layer 110 may include a dielectric material. For example, the device isolation layer 110 may include silicon oxide. The device isolation layer 110 may define active regions AR of the substrate 100. Each of the active regions AR may have an elongated bar shape. The active regions AR may extend in a first direction D1. The active regions AR may be parallel to each other.

A source/drain region may be provided in each of the active regions AR of the substrate 100. The source/drain region may have a conductivity type different from that of the substrate 100. For example, when the substrate 100 has p-type conductivity, the source/drain region may have n-type conductivity.

A pair of word lines WL may be provided on each of the active regions AR of the substrate 100. The word lines WL may extend in a second direction D2 that intersects the first direction D1. The second direction D2 may not be perpendicular to the first direction D1. The word lines WL may run across the active regions AR. The word lines WL may be embedded in the active regions AR of the substrate 100. For example, the word lines WL may have their top surfaces at a level that is lower than that of a top surface of the substrate 100. The word lines WL may include a conductive material. For example, the word lines WL may include doped polysilicon, metal, or metal silicide. Although not shown, a gate dielectric pattern may be provided between the substrate 100 and a sidewall of each of the word lines WL and between the substrate 100 and a bottom surface of each of the word lines WL. In addition, a capping pattern may be provided between the top surface of the substrate 100 and the top surface of each of the word lines WL. The gate dielectric pattern and the capping pattern may include, for example, silicon oxide.

A buffer pattern 121 may be provided on the top surface of the substrate 100. The buffer pattern 121 may include a single-layered dielectric material or a multi-layered stacked dielectric material. For example, the buffer pattern 121 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

First contacts DCC may be provided on the active regions AR of the substrate 100. Each first contact DCC may be a bit-line node contact. Each first contact DCC may penetrate the buffer pattern 121 and may extend in a fourth direction D4 that is perpendicular to the first and second directions D1 and D2. Each first contact DCC may be electrically connected to the source/drain region that is provided in each of the active regions AR of the substrate 100. Each first contact DCC may include a conductive material. For example, each first contact DCC may include one or more of metal, metal nitride, metal silicide, and poly silicide (or polysilicon silicide).

Bit-line structures BLS may be provided to run across the active regions AR of the substrate 100 in a third direction D3 intersecting the first and second directions D1 and D2. The third direction D3 may be perpendicular to the first and fourth directions D1 and D4. The bit-line structures BLS may be spaced apart from each other in the second direction D2. Each bit-line structure BLS may be in contact with a first contact DCC or the buffer pattern 121. A bit-line structure BLS may be electrically connected to a respective first contact DCC.

Each of the bit-line structures BLS may include a bit line BL and a first dielectric pattern 220 that are sequentially stacked on the substrate 100. The bit line BL may include a first conductive pattern 212 and a second conductive pattern 214. The second conductive pattern 214 may be provided between the first conductive pattern 212 and the first dielectric pattern 220. The first conductive pattern 212 may include, for example, polysilicon or doped polysilicon. The second conductive pattern 214 may include, for example, one of tungsten (W), aluminum (Al), copper (Co), nickel (Ni), and cobalt (Co). The first dielectric pattern 220 may include, for example, silicon oxide. Although not shown, a diffusion break layer may be interposed between the first conductive pattern 212 and the second conductive pattern 214.

A second contact BC may be provided on an end of each active region AR of the substrate 100 between adjacent bit-line structures BLS. The second contact BC may be a storage node contact. The second contact BC may extend in the fourth direction D4 on the active region AR of the substrate 100. The second contact BC may have a maximum width L2 in the second direction D2 that is greater than a width L1 in the second direction D2 of each of the active regions AR. The second contact BC may include a first buried contact 311 and a second buried contact 351. The first buried contact 311 and the second buried contact 351 may include, for example, one or more of metal, metal nitride, metal silicide, and polysilicon. For example, the first buried contact 311 and the second buried contact 351 may include substantially the same material.

The first buried contact 311 may be provided on one of the active regions AR of the substrate 100 and on the device isolation layer 110 in the vicinity of the one of the active regions AR. The first buried contact 311 may have a sidewall that is in contact with the device isolation layer 110. The first buried contact 311 may be electrically connected to the source/drain region that is provided in each of the active regions AR of the substrate 100. The first buried contact 311 may have a bottom surface at a level higher than that of a bottom surface of the first contact DCC. The first buried contact 311 may have a top surface with a portion that is concave.

The second buried contact 351 may be provided between adjacent bit-line structures BLS. The second buried contact 351 may have a top surface at a level lower than that of a top surface of the first dielectric pattern 220. The second buried contact 351 may be in partial contact with the top surface of the first buried contact 311. The second buried contact 351 may have a bottom surface with a portion that is convex toward the first buried contact 311. The convex portion of the bottom surface of the second buried contact 351 may abut or may be adjacent to the concave portion of the top surface of the first buried contact 311.

A spacer structure SPS may be provided between the bit-line structures BLS and the second buried contact 351, between the first contact DCC and the second buried contact 351, and between the first contact DCC and the first buried contact 311. The spacer structure SPS may include first, second, and third spacers SP1, SP2, and SP3. The first, second, and third spacers SP1, SP2, and SP3 may extend in the fourth direction D4 on sidewalls of the bit-line structures BLS and on at least one sidewall of the first contact DCC. In addition, the second and third spacers SP2 and SP3 may extend in the fourth direction D4 on the sidewalls of the bit-line structures BLS, on a sidewall of the buffer pattern 121, and on an outer wall 111 of the device isolation layer 110. The second spacer SP2 may be provided between the first spacer SP1 and the third spacer SP3. The first, second, and third spacers SP1, SP2, and SP3, which are provided on facing sidewalls of adjacent bit-line structures BLS, may be spaced apart in the second direction D2 from each other across the second buried contact 351. The second and third spacers SP2 and SP3 may have their bottom surfaces at levels that are lower than that of an uppermost surface of the device isolation layer 110 within the substrate 100. The first and third spacers SP1 and SP3 may include silicon nitride, as an example. In some embodiments, the second spacer SP2 may include silicon oxide or may be an air gap.

The first spacer SP1 may be provided on the sidewall of the bit-line structure BLS and on the sidewall of the first contact DCC. The first spacer SP1 may have a bottom surface that is in contact with either the buffer pattern 121 or the device isolation layer 110. The bottom surface of the first spacer SP1 that is in contact with the buffer pattern 121 may be coplanar with the top surface of the buffer pattern 121 and with a bottom surface of the first conductive pattern 212 of the bit line BL. The bottom surface of the first spacer SP1 that is in contact with the device isolation layer 110 may be coplanar with the bottom surface of the first contact DCC. In addition, the bottom surface of the first spacer SP1 that is in contact with the device isolation layer 110 may be located at a level lower than that of the bottom surface of the first buried contact 311 included in the second contact BC. The first spacer SP1 that is in contact with the device isolation layer 110 may be J-shaped when viewed in cross-section. For example, the first spacer SP1 in contact with the device isolation layer 110 may include a first segment SP1 a and a second segment SP1 b. The first segment SP1 a may extend in the fourth direction D4 on sidewalls of the first dielectric pattern 220, the bit line BL, and the first contact DCC. The second segment SP1 b may cover a top surface of the device isolation layer 110. The second segment SP1 b may have a curved shape that extends along the top surface of the device isolation layer 110.

A first sub-spacer 234 and a second sub-spacer 236 may be provided between the first and second segments SP1 a and SP1 b of the first spacer SP1. The first sub-spacer 234 may conform to and cover a sidewall and a bottom surface of a space that is surrounded by the first spacer SP1 and the second spacer SP2. The second sub-spacer 236 may fill a space that is surrounded by the first sub-spacer 234 and the second spacer SP2. For example, the first and second sub-spacers 234 and 236 may have their top surfaces at a level higher than that of the top surface of the first buried contact 311. The first sub-spacer 234 may include, for example, silicon oxide. The second sub-spacer 236 may include, for example, silicon nitride.

The second spacer SP2 may be provided on a sidewall of the first spacer SP1. The second spacer SP2 may include a segment that extends in the second direction D2 and a segment that extends in the fourth direction D4. The bottom surface of the second spacer SP2 may be in contact either with the top surface of the first buried contact 311 or with a top surface of the second segment SP1 b and the top surfaces of the first and second sub-spacers 234 and 236. The second spacer SP2 in contact with the top surface of the first buried contact 311 may be in contact with the sidewall of the first spacer SP1, the sidewall of the buffer pattern 121, and the outer wall 111 of the device isolation layer 110. For example, the second spacer SP2 may extend along the sidewall of the first spacer SP1, the sidewall of the buffer pattern 121, and the outer wall 111 of the device isolation layer 110. The second spacer SP2 may have a top surface that is in contact with a third dielectric pattern 396 of a second separation pattern 390. The second spacer SP2 may include, for example, silicon oxide.

The third spacer SP3 may be provided on a sidewall of the second spacer SP2. A portion of the third spacer SP3 may be provided between the second spacer SP2 and a barrier pattern 391 of a landing pad LP. Another portion of the third spacer SP3 may be provided between the second spacer SP2 and the second buried contact 351. The bottom surface of the third spacer SP3 may be in contact with a portion of the second spacer SP2, The portion of the second spacer SP2 in contact with the bottom surface of the third spacer SP3 extends in the second direction D2. The third spacer SP3 may be spaced apart from the first buried contact 311 across the portion, which extends in the second direction D2, of the second spacer SP2. The third spacer SP3 may have a top surface at a level that is higher than that of a top surface of the second conductive pattern 214 included in the bit line BL. The top surface of the third spacer SP3 may be in contact with the barrier pattern 391 of the landing pad LP. The third spacer SP3 may include, for example, silicon nitride.

A second dielectric pattern 371 may be provided between the second spacer SP2 and the barrier pattern 391 of the landing pad LP. The second dielectric pattern 371 may be in contact with the top surface of the third spacer SP3. The second dielectric pattern 371 may have a bottom surface at a level that is higher than that of the top surface of the second conductive pattern 214 included in the bit line BL. The second dielectric pattern 371 may include, for example, silicon nitride.

From a different point of view, the spacer structure SPS may include a first part SPS1 that is in contact with the first contact DCC and a second part SPS2 that is between adjacent first parts SPS1. The first part SPS1 and the second part SPS2 may be spaced apart in the second direction D2 from each other across the second contact BC. The first part SPS1 may have a bottom surface coplanar with that of the first contact DCC. The first part SPS1 may be in contact with at least a portion of bottom surface of the second contact BC. The second part SPS2 may have a bottom surface that is in contact with the second contact BC. The bottom surface of the second part SPS2 may be located at a level that is lower than that of the uppermost surface of the device isolation layer 110.

A first separation pattern 250 may be provided at an intersection where the word line WL intersects a zone between adjacent bit-line structures BLS. The first separation pattern 250 may include, for example, one or more of SiBCN, SiCN, SiOCN, and SiN.

The landing pad LP may be provided on the top surface of the second buried contact 351. The landing pad LP may be electrically connected to the second buried contact 351 of the second contact BC. A portion of the landing pad LP may be provided on a top surface of one of the bit-line structures BLS adjacent to the landing pad LP. For example, the landing pad LP may have a top surface at substantially the same level as that of a top surface of the first separation pattern 250.

The landing pad LP may include a barrier pattern 391 and a third conductive pattern 393 that are sequentially stacked on the second buried contact 351. The barrier pattern 391 may be provided between the third conductive pattern 393 and the second buried contact 351, between the third conductive pattern 393 and the first to third spacers SP1 to SP3, and between the third conductive pattern 393 and a portion of the top surface of the first dielectric pattern 220. The barrier pattern 391 may include, for example, TiN, Ti/TiN, TiSiN, TaN, or WN. The third conductive patterns 393 may include metal. For example, the third conductive pattern 393 may include tungsten (W).

The second separation pattern 390 may be provided between adjacent landing pads LP. The second separation pattern 390 may surround a sidewall of the landing pad LP. A portion of the second separation pattern 390 may be embedded in the first dielectric pattern 220. The second separation pattern 390 may have a bottom surface that is provided between the top and bottom surfaces of the first dielectric pattern 220. The bottom surface of the second separation pattern 390 may be in partial contact with the first and second spacers SP1 and SP2. The second separation pattern 390 may have a top surface at substantially the same level as that of the top surface of the landing pad LP. For example, the top surface of the second separation pattern 390 may be coplanar with the top surface of the landing pad LP. The second separation pattern 390 may include a third dielectric pattern 396 and a fourth dielectric pattern 398. The third dielectric pattern 396 may be in contact with the sidewall of the landing pad LP, a portion of the sidewall of the first dielectric pattern 220, and the top surfaces of the first and second spacers SP1 and SP2. The third dielectric pattern 396 may include, for example, tetraethyl orthosilicate (TEOS) or high density plasma (HDP) oxide. The fourth dielectric pattern 398 may be disposed in a space that is surrounded by the third dielectric pattern 396. The fourth dielectric pattern 398 may include, for example, silicon oxide or silicon nitride.

A data storage element may be provided on the landing pad LP. The data storage element may be, for example, a capacitor. The capacitors that overlap in the fourth direction D4 with one of the bit-line structures BLS may be arranged in a zigzag fashion along the third direction D3. Each of the capacitors may include a bottom electrode BE, a dielectric layer, and a top electrode. The bottom electrode BE may extend in the fourth direction D4 from the top surface of the landing pad LP.

FIGS. 2A to 18A illustrate operations of methods for fabricating semiconductor devices according to some example embodiments of the present inventive concepts. FIGS. 2B to 18B illustrate cross-sectional views taken along line I-I′ of FIGS. 2A to 18A, respectively, showing operations of methods for fabricating semiconductor devices according to some example embodiments of the present inventive concepts.

Referring to FIGS. 2A and 2B, a device isolation layer 110 may be formed in a substrate 100. The device isolation layer 110 may define active regions AR. The active regions AR may extend in a first direction D1 when viewed in a plan view and in a fourth direction D4 when viewed in cross-section. The device isolation layer 110 may be formed by forming trenches on the substrate 100 and filing the trenches with a dielectric material.

A source/drain region may be formed in each of the active regions AR. A source/drain region may be formed by forming an ion implantation mask on the substrate 100 and performing an ion implantation process on the substrate 100 exposed by the ion implantation mask. Alternatively, the ion implantation process may be carried out without the ion implantation mask.

Referring to FIGS. 3A and 3B, word lines WL may be formed in the substrate 100. The word lines WL may be formed by forming trenches in the substrate 100, forming a gate dielectric pattern to conformally cover surfaces of the trenches, forming a metal layer to fill the trenches surrounded by the gate dielectric pattern, and partially etching the metal layer. A capping pattern may be additionally formed on each of the word lines WL. The capping pattern may completely fill the trench in which the word line WL is formed.

A buffer layer 120 may be formed on the substrate 100. The buffer layer 120 may be formed of a single-layered dielectric material or a multi-layered stacked dielectric material. The buffer layer 120 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The substrate 100 and the buffer layer 120 may be patterned to form a first contact hole CH1. The first contact hole CH1 may be formed by forming a mask pattern on the buffer layer 120 and partially etching the buffer layer 120 and the substrate 100 that are exposed by the mask pattern. The first contact hole CH1 may expose a sidewall of the buffer layer 120, a top surface of one of the active regions AR, and a portion of the device isolation layer 110.

Referring to FIGS. 4A and 4B, a contact pattern 130 may be formed in the first contact hole CH1. The contact pattern 130 may completely fill the first contact hole CH1. For example, the contact pattern 130 may be formed by forming on the buffer layer 120 a conductive layer to fill the first contact hole CH1 and performing on the conductive layer a planarization process until a top surface of the buffer layer 120 is exposed. The planarization process may be, for example, a chemical mechanical polishing (CMP) process or an etch-back process. The contact pattern 130 may include, for example, one or more of metal, metal nitride, metal silicide, and poly silicide (polysilicon silicide).

Referring to FIGS. 5A and 5B, a conductive layer 210 may be formed on the buffer layer 120. The conductive layer 210 may include a multi-layered stacked conductive material. For example, the conductive layer 210 may include a first conductive layer 211 and a second conductive layer 213 that are sequentially stacked on the buffer layer 120. The first conductive layer 211 may include, for example, polysilicon or doped polysilicon. The second conductive layer 213 may include, for example, one of tungsten (W), aluminum (Al), copper (Co), nickel (Ni), and cobalt (Co). Although not shown, a diffusion break layer may be interposed between the first conductive layer 211 and the second conductive layer 213. The diffusion break layer may include a diffusion barrier metal. The diffusion break layer may include, for example, TiN, Ti/TiN, TiSiN, TaN, or WN.

A first dielectric pattern 220 may be formed on the second conductive layer 213. The first dielectric pattern 220 may be formed by forming a first dielectric layer on the second conductive layer 213 and patterning the first dielectric layer. The first dielectric pattern 220 may extend in a third direction D3. The first dielectric pattern 220 may include a plurality of patterns that are formed parallel to each other. The plurality of patterns may be spaced apart from each other in a second direction D2. The first dielectric pattern 220 may run across the active regions AR, crossing over the contact pattern 130.

Referring to FIGS. 6A and 6B, the conductive layer 210 may be patterned to form bit lines BL. For example, the first conductive layer 211 and the second conductive layer 213 may be patterned to form a first conductive pattern 212 and a second conductive pattern 214. The contact pattern 130 may be patterned to form a first contact DCC. The first dielectric pattern 220 may be used as an etching mask to pattern the conductive layer 210 and the contact pattern 130. The patterning process may expose a portion of the top surface of the buffer layer 120, a portion of the top surface of one of the active regions AR, and a portion of the device isolation layer 110. The bit line BL may run across the active regions AR in the third direction D3 to cross over the first contact DCC. The first conductive pattern 212, the second conductive pattern 214, and the first dielectric pattern 220 may constitute a bit-line structure BLS.

Referring to FIGS. 7A and 7B, a spacer layer structure 230 may be formed to conform to and cover a sidewall of the first conductive pattern 212, a sidewall of the second conductive pattern 214, a sidewall and a top surface of the first dielectric pattern 220, a top surface of the buffer layer 120, a sidewall of the first contact DCC, and a surface of the first contact hole CH1. The surface of the first contact CH1 on which the spacer layer structure 230 is formed may be a side surface of the device isolation layer 110. The spacer layer structure 230 may include, for example, silicon nitride.

The spacer layer structure 230 may include first, second, and third spacer layers 231, 233, and 235. The first spacer layer 231 may be formed on the sidewall of the first conductive pattern 212, the sidewall of the second conductive pattern 214, the sidewall and a top surface of the first dielectric pattern 220, the top surface of the buffer layer 120, the sidewall of the first contact DCC, and the surface of the first contact hole CH1. The second spacer layer 233 and the third spacer layer 235 may be sequentially formed on the first spacer layer 231. The second spacer layer 233 may be formed to conform to and cover a surface of the first spacer layer 231. The third spacer layer 235 may be formed to conform to and cover a surface of the second spacer layer 233. The second and third spacer layers 233 and 235 may fill the first contact hole CH1 that is partially filled with the first contact DCC. The second and third spacer layers 233 and 235 may include a material having an etch selectivity with respect to the first spacer layer 231.

Referring to FIGS. 8A and 8B, the second and third spacer layers (see 233 and 235 of FIG. 7B) may be etched. Therefore, the first spacer layer 231 may be exposed at a top surface thereof. In contrast, portions of the second and third spacer layers (see 233 and 235 of FIG. 7B) inside the first contact hole CH1 may not be etched.

Referring to FIGS. 9A and 9B, an etching process may be performed to partially etch a zone between adjacent bit-line structures BLS. The etching process may etch only a portion of the top surface of the first spacer layer (see 231 of FIG. 8B) formed on sidewalls of the bit-line structures BLS. Therefore, the first dielectric pattern 220 may be exposed at the top surface thereof. The etching process may form a first spacer SP1, a buffer pattern 121, a first sub-spacer 234, and a second sub-spacer 236. In addition, the etching process may form a second contact hole CH2. The second contact hole CH2 may expose a sidewall of the first spacer SP1, a sidewall of the buffer pattern 121, a portion of a top surface of the active region AR, a portion of a top surface of the device isolation layer 110, a top surface of the first sub-spacer 234, and a top surface of the second sub-spacer 236.

A first separation pattern 250 may be formed at an intersection where the word line WL intersects a zone between adjacent bit-line structures BLS. The first separation pattern 250 may be formed by forming a dielectric material to fill the zone between adjacent bit-line structures BLS, forming first openings OP1 by etching the dielectric material that fills the intersection where the word line WL intersects the zone between adjacent bit-line structures BLS, filling the first openings OP1 with a material having an etch selectivity with respect to the dielectric material, and etching the dielectric material formed on areas except in the first openings OP1.

Referring to FIGS. 10A and 10B, an etching process may be performed to partially etch the active regions AR. The etching process may be, for example, an ion plasma etching (IPE) process. In addition, the device isolation layer 110 may be partially recessed. The active regions AR and the device isolation layer 110 may be partially removed to form a third contact hole CH3. The third contact hole CH3 may be spaced apart from the first and second sub-spacers 234 and 236. The third contact hole CH3 may expose the device isolation layer 110 and the active regions AR.

Referring to FIGS. 11A and 11B, a first buried contact 310 may be formed in the third contact hole CH3. The first buried contact 310 may be formed by forming a conductive material to fill the third contact hole CH3 and a zone between adjacent bit-line structures BLS and then performing an etch-back process to etch the conductive material. The first buried contact 310 may have a top surface that is parallel to a bottom surface of the substrate 100. For example, the top surface of the first buried contact 310 may be flat. The top surface of the first buried contact 310 may be located at a level that is lower than those of the top surfaces of the first and second sub-spacers 234 and 236. The first buried contact 310 may have a bottom surface at a level higher than that of a bottom surface of the first contact DCC. The bottom surface of the first buried contact 310 may have a width in the second direction D2 greater than a width in the second direction D2 of each of the active regions AR. For example, the first buried contact 310 may be formed to cover the active region AR. The active region AR may not be exposed due to the first buried contact 310. The first buried contact 310 may be electrically connected to the active region AR. Before the formation of spacers, the third contact hole CH3 may be formed and the first buried contact 310 may be formed to fill the third contact hole CH3, which may result in an increase in contact area between the first buried contact 310 and the active region AR.

Referring to FIGS. 12A and 12B, a fourth spacer layer 331 and a fifth spacer layer 333 may be formed to conformally cover the top surface of the first dielectric pattern 220, the sidewall of the first spacer SP1, a sidewall of the buffer pattern 121, a sidewall of a portion of the device isolation layer 110, a top surface of the first buried contact 310, and the top surfaces of the first and second sub-spacers 234 and 236. The fourth spacer layer 331 may include, for example, silicon oxide. The fifth spacer layer 333 may include, for example, silicon nitride. The formation of the first buried contact 310 may be followed by the formation of the fourth and fifth spacer layers 331 and 333, and as a result, voids may be prevented from being formed in the first buried contact 310.

Referring to FIGS. 13A and 13B, an etching process may be performed to partially etch the fourth and fifth spacer layers (see 331 and 333 of FIG. 12B), a top surface of the first buried contact (see 310 of FIG. 12B), and the first spacer SP1 adjacent to the second sub-spacer 236. Therefore, the first dielectric pattern 220 may be exposed at the top surface thereof. The etching process may form a second spacer SP2 and a sixth spacer layer 334. In addition, the etching process may form a fourth contact hole CH4. The partially etched first buried contact 310, or a first buried contact 311, may have a top surface whose lowermost point is located at a level lower than that of a bottom surface of the second spacer SP2. In this case, forming the fourth contact hole CH4 may result in a top surface of the first buried contact 311 being concave.

Referring to FIGS. 14A and 14B, a second buried contact 350 may be formed in the fourth contact hole CH4. The second buried contact 350 may be formed by filling the fourth contact hole CH4 with a conductive material and performing an etch-back process to etch the conductive material. The second buried contact 350 may have a top surface that is parallel to the bottom surface of the substrate 100. For example, the top surface of the second buried contact 350 may be flat. In this case, the top surface of the second buried contact 350 may be located at a level that is higher than that of a top surface of the second conductive pattern 214 of the bit line BL. The second buried contact 350 may be in partial contact with the top surface of the first buried contact 311. The bottom surface of the second buried contact 350 may be convex toward the first buried contact 311.

The sixth spacer layer (see 334 of FIG. 13B) may be partially etched to form a third spacer SP3. Therefore, the second spacer SP2 may be exposed at a sidewall thereof. The third spacer SP3 may have a top surface that is at substantially the same level as that of the top surface of the second buried contact 350. For example, the top surface of the third spacer SP3 may be coplanar with the top surface of the second buried contact 350.

Referring to FIGS. 15A and 15B, a second dielectric layer 370 may be formed to conformally cover the top surface of the first dielectric pattern 220, the top surfaces of the first, second, and third spacers SP1, SP2, and SP3, the sidewall of the second spacer SP2, and the top surface of the second buried contact 350. The second dielectric layer 370 may include, for example, silicon nitride.

Referring to FIGS. 16A and 16B, the second dielectric layer (see 370 of FIG. 15B) may be patterned to form a second dielectric pattern 371. The second dielectric pattern 371 may have a thickness in the second direction D2 that is less than a thickness of the third spacer SP3 in the second direction D2. Neither the top surface nor the sidewall of the second spacer SP2 may be externally exposed due to the second dielectric pattern 371.

The second buried contact (see 350 of FIG. 15B) may also be partially etched. Therefore, the partially etched second buried contact 350, or a second buried contact 351, may have a top surface at a level that is lower than that of the top surface of the third spacer SP3. For example, the top surface of the second buried contact 351 may be located at substantially the same level as that of the top surface of the second conductive pattern 214 included in the bit line BL.

Referring to FIGS. 17A and 17B, a landing pad LP may be formed on the second buried contact 351. The landing pad LP may be formed by sequentially stacking a barrier layer and a conductive layer, and then performing a patterning process on the barrier layer and the conductive layer. The barrier layer may conform to and cover the top surface of the second buried contact 351, the top surfaces of the first, second, and third spacers SP1, SP2, and SP3, and the top surface of the first dielectric pattern 220, and a top surface of the second dielectric pattern 371. The conductive layer may be formed on the barrier layer. The patterning process may form a second opening OP2. A barrier pattern 391 and a third conductive pattern 393 may be formed so as to be spaced apart in the second direction D2 across the second opening OP2. The second opening OP2 may expose a portion of the first dielectric pattern 220, a portion of the second dielectric pattern 371, and the top surfaces of the first and second spacers SP1 and SP2.

Although not shown, the second spacer SP2 which is exposed to the second opening OP2 may be selectively removed. The selective removal of the second spacer SP2 may form an empty space between the first spacer SP1 and the third spacer SP3. The selective removal of the second spacer SP2 may be achieved by performing, for example, a wet etching process that uses an etching solution. The etching solution may include, for example, hydrofluoric acid (HF). Because the empty space is formed between the first spacer SP1 and the third spacer SP3, a parasitic capacitance may be reduced between the second contact BC and the bit line BL.

Referring to FIGS. 18A and 18B, a third dielectric layer 395 and a fourth dielectric layer 397 may be sequentially formed on the landing pad LP. The third dielectric layer 395 may conform to and cover a sidewall and a bottom surface of the second opening OP2 and also cover a top surface of the third conductive pattern 393. For example, the third dielectric layer 395 may cover a portion of the first dielectric pattern 220, a portion of the second dielectric pattern 371, and the top surface of the first and second spacers SP1 and SP2. The fourth dielectric layer 397 may completely fill the second opening OP2 that is partially filled with the third dielectric layer 395. The third dielectric layer 395 may include, for example, tetraethyl orthosilicate (TEOS) or high density plasma (HDP) oxide. The fourth dielectric layer 397 may include, for example, silicon oxide or silicon nitride.

Referring back to FIGS. 1A to 1C, a planarization process may be performed to expose the top surface of the third conductive pattern 393 included in the landing pad LP. Thus, a second separation pattern 390 may be formed in the second opening OP2. The second separation pattern 390 may include a third dielectric pattern 396 and a fourth dielectric pattern 398 that is surrounded by the third dielectric pattern 396. The third and fourth dielectric patterns 396 and 398 may have their top surfaces coplanar with the top surface of the third conductive pattern 393 of the landing pad LP.

A bottom electrode BE may be formed on the top surface of the third conductive pattern 393 of the landing pad LP. Although not shown, a dielectric layer and a top electrode may further be formed in addition to the bottom electrode BE. The bottom electrode BE, the dielectric layer, and the top electrode may constitute a data storage element. The data storage element may be, for example, a capacitor.

FIG. 19 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts. FIGS. 20 and 21 illustrate cross-sectional views showing operations of methods of fabricating semiconductor devices according to some example embodiments of the present inventive concepts. The description of features substantially the same as those discussed above with reference to FIGS. 1A to 18B will be omitted for the purpose of convenience in explanation.

Referring to FIG. 19, a semiconductor device according to some embodiments of the present inventive concepts may include the second buried contact 351 being in partial contact with the top surface of one of the active regions AR. The second buried contact 351 may be a storage node contact. In this sense, the second buried contact 351 may correspond to the second contact BC of FIG. 1B. The second buried contact 351 may have a bottom surface whose shape is convex so as to conform to a shape of the third contact hole CH3. The second buried contact 351 may not overlap in the fourth direction D4 with the bottom surfaces of the second and third spacers SP2 and SP3. The bottom surface of the second buried contact 351 may be located at a level higher than that of the bottom surface of the first contact DCC. The bottom surface of the second buried contact 351 may have a lowermost point that is located at a level lower than those of the bottom surfaces of the second and third spacers SP2 and SP3. The bottom surfaces of the first, second, and third spacers SP1, SP2, and SP3 may be located at a level that is lower than that of the uppermost surface of the device isolation layer 110 in the substrate 100.

Referring to FIGS. 9B and 20, the fourth spacer layer 331 may be formed to conform to and cover the top surface of the first dielectric pattern 220, the sidewall and the top surface of the first spacer SP1, the sidewall of the buffer pattern 121, the top surfaces of the active regions AR, a portion of the top surface of the device isolation layer 110, and the top surfaces of the first and second sub-spacers 234 and 236, and the fifth spacer layer 333 may be formed to conform to and cover the fourth spacer layer 331.

Referring to FIG. 21, an etching process may be performed to partially etch the fourth and fifth spacer layers (see 331 and 333 of FIG. 20), the active regions AR, and the device isolation layer 110. The etching process may form the second spacer SP2 and the sixth spacer layer 334. In addition, the etching process may form the third contact hole CH3. The third contact hole CH3 may be formed to have a convex bottom surface. Because the formation of the second spacer SP2 and the sixth spacer layer 334 is followed by the formation of the third contact hole CH3, voids may be prevented from being formed on the bottom surfaces of the first and second spacers SP1 and SP2.

Subsequent processes may be substantially the same as those discussed above with reference to FIGS. 14A to 18B.

FIG. 22 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the present inventive concepts. FIGS. 23 and 24 illustrate cross-sectional views showing operations of methods of fabricating semiconductor devices according to some example embodiments of the present inventive concepts. The description of features substantially the same as those discussed above with reference to FIGS. 1A to 21 will be omitted for the purpose of convenience in explanation.

Referring to FIG. 22, a semiconductor device according to some embodiments of the present inventive concepts may include the first buried contact 311 that penetrates a portion of the first spacer SP1 and the first sub-spacer 234. The first buried contact 311 and the second buried contact 351 may be integrally connected to form a storage node contact. The bottom surface of the first buried contact 311 may be flat to conform to a shape of the third contact hole CH3. The bottom surface of the second buried contact 351 may be convex to conform to a shape of the fourth contact hole CH4. The first buried contact 311 may overlap in the fourth direction D4 with the bottom surfaces of the first and second spacers SP2 and SP3. The bottom surface of the first buried contact 311 may be located at a level that is higher than that of the bottom surface of the first contact DCC. The bottom surface of the first buried contact 311 may be located at a level that is lower than those of the bottom surfaces of the second and third spacers SP2 and SP3. The bottom surface of the first buried contact 311 may be in contact with the first spacer SP1. The bottom surfaces of the first, second, and third spacers SP1, SP2, and SP3 may be located at a level lower than that of the uppermost surface of the device isolation layer 110 in the substrate 100.

Referring to FIGS. 9B and 23, the active regions AR may be partially etched. The device isolation layer 110, the first spacer SP1, and the first and second sub-spacers 234 and 236 may be partially recessed. The active regions AR, the device isolation layer 110, the first spacer SP1, and the first and second sub-spacers 234 and 236 may be partially removed to form the third contact hole CH3. The third contact hole CH3 may be defined by a portion of the sidewall of the second sub-spacer 236, a portion of the top surface of the first sub-spacer 234, a portion of the top surface of the first spacer SP1, portions of the sidewall and the top surface of the device isolation layer 110, and one of the active regions AR.

Referring to FIG. 24, the first buried contact 310 may be formed in the third contact hole CH3. The top surface of the first buried contact 310 may be located at a level higher than those of the top surfaces of the first and second sub-spacers 234 and 236.

Subsequent processes may be substantially the same as those discussed above with reference to FIGS. 12A to 18B.

According to some example embodiments of the present inventive concepts, an increased contact area may be provided between an active region and a storage node contact that includes one or more buried contacts, and thus a semiconductor device may have improved electrical characteristics.

Furthermore, in method of fabricating semiconductor devices according to some example embodiments of the present inventive concepts, because the formation of a spacer is preceded by the formation of a buried contact that contacts an active contact, voids may be prevented from being formed below the spacer, with the result that the fabricated semiconductor devices may have improved electrical characteristics.

Although the present inventive concepts have been described in connection with some example embodiments thereof illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the scope of the present inventive concepts. The above disclosed embodiments should thus be considered illustrative and not restrictive. 

What is claimed is:
 1. A method of fabricating a semiconductor device, the method comprising: forming, on a substrate, a device isolation layer that defines a plurality of active regions; forming a plurality of word lines on the substrate; forming a first contact hole by etching a portion of the substrate; forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole; forming a plurality of bit-line structures by etching the contact pattern and the conductive layer; forming a second contact hole by etching the active regions between the bit-line structures; forming a first buried contact in a lower portion of the second contact hole; forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and forming a second buried contact between the spacer structures, wherein the forming of the spacer structures comprises: forming a first spacer that covers each of the sidewalls of the bit-line structures; forming a second spacer that covers a sidewall of the first spacer; and forming a third spacer that covers a sidewall of the second spacer, and wherein the second spacer is in contact with a portion of an outer wall of the device isolation layer.
 2. The method of claim 1, wherein the second spacer extends from the sidewall of the first spacer to the outer wall of the device isolation layer.
 3. The method of claim 1, further comprising forming a buffer pattern, wherein the forming of the buffer pattern comprises: forming a buffer layer on the active regions and the device isolation layer, and patterning the buffer layer.
 4. The method of claim 3, wherein the second spacer extends from the sidewall of the first spacer to a sidewall of the buffer pattern.
 5. The method of claim 3, wherein the forming of the first spacer comprises: forming a first spacer layer covering the sidewalls of the bit-line structures and a top surface of the buffer layer; and etching a portion of the first spacer layer.
 6. The method of claim 1, wherein the first buried contact is in contact with each of top surfaces of the active regions.
 7. The method of claim 1, wherein the forming of the second contact hole comprises etching the device isolation layer that surrounds the active regions between the bit-line structures.
 8. The method of claim 1, wherein the forming of the second spacer and the third spacer comprises: forming a second spacer layer and a third spacer layer on the sidewall of the first spacer and a top surface of the first buried contact; and etching a portion of the second spacer layer and a portion of the third spacer layer.
 9. The method of claim 1, wherein the second spacer is interposed between the first spacer and the third spacer.
 10. A method of fabricating a semiconductor device, the method comprising: forming, on a substrate, a device isolation layer that defines a plurality of active regions; forming a plurality of word lines on the substrate; forming a first contact hole by etching a portion of the substrate; forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole; forming a plurality of bit-line structures by etching the contact pattern and the conductive layer; forming a second contact hole by etching the active regions between the bit-line structures; forming a first buried contact in a lower portion of the second contact hole; forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and forming a second buried contact between the spacer structures, wherein the forming of the spacer structures comprises: forming a first spacer covering each of the sidewalls of the bit-line structures; forming a second spacer covering a sidewall of the first spacer; and forming a third spacer covering a sidewall of the second spacer, and wherein the second spacer is in contact with a top surface of the first buried contact.
 11. The method of claim 10, wherein the forming of the spacer structures comprises enlarging the second contact hole by etching a portion of the first buried contact.
 12. The method of claim 10, wherein the second spacer includes a lower portion on the top surface of the first buried contact, and a upper portion vertically extending from the lower portion.
 13. The method of claim 12, wherein the third spacer is provided on a top surface of the lower portion and a sidewall of the upper portion.
 14. The method of claim 12, wherein the third spacer is spaced apart from the first buried contact with the lower portion of the second spacer interposed therebetween.
 15. The method of claim 10, wherein the top surface of the first buried contact comprises a first surface being in contact with the second spacer and a second surface being in contact with the second buried contact, and wherein the first surface is a flat surface and the second surface is a concave surface.
 16. A method of fabricating a semiconductor device, the method comprising: forming, on a substrate, a device isolation layer that defines a plurality of active regions; forming a plurality of word lines on the substrate; forming a first contact hole by etching a portion of the substrate; forming a contact pattern and a conductive layer on the contact pattern, wherein the contact pattern is within the first contact hole; forming a plurality of bit-line structures by etching the contact pattern and the conductive layer; forming a second contact hole by etching the active regions between the bit-line structures; forming a first buried contact in a lower portion of the second contact hole; forming a plurality of spacer structures that cover sidewalls of the bit-line structures; and forming a second buried contact between the spacer structures, wherein the forming of the spacer structures comprises: forming a first spacer covering each of the sidewalls of the bit-line structures; forming a second spacer covering a sidewall of the first spacer; and forming a third spacer covering a sidewall of the second spacer, and wherein a top surface of the third spacer is located at a lower level than a top surface of the first spacer and a top surface of the second spacer.
 17. The method of claim 16, further comprising forming a dielectric pattern on the third spacer.
 18. The method of claim 17, wherein the forming of the dielectric pattern comprises: forming a dielectric layer on a portion of the sidewall of the second spacer, the top surface of the third spacer, and a top surface of the second buried contact, and patterning the dielectric layer.
 19. The method of claim 17, wherein a sidewall of the dielectric pattern is spaced apart from a sidewall of the third spacer.
 20. The method of claim 16, wherein the third spacer is spaced apart from the first buried contact with the second spacer interposed therebetween. 